My first synthesizable verilog module (combinational)

Here I am going to explain about the simulation of a simple synthesizable combinational module. What is synthesizable ? I will tell you in detail later.

Now keep in mind that each and every verilog module cannot be ported to fpga or asic, such as the module having for loop, while loop etc.

A simple adder module is given below.

module adder (
input [7:0] in1, //input one 8 bit width
input [7:0] in2, //input two
output [8:0] out //output sum 9bit
);

assign out = in1 + in2 ; //assigns sum to out

endmodule

A module can be considered as an IC. A module communicates with outside world through ports. Data is passed to the module using input port and the result is available on output port. Here two inputs are present, in1 and in2, having a width of 8 bit. We apply input data to be added on in1 and in2. The sum is available on output port out.

Inorder to check the functionality of the module we need to supply the input and monitor the output right. The perform these functions the module is put inside another module called testbench.

The testbench supplies the data and checks or displays the result.First I will give the testbench and then I will explain.

module adder_test ;

reg [7:0] in1 ; //declaration of register in1
reg [7:0] in2 ; //declaration of register in2
wire [8:0] out ; //declaration of wire out

adder adder_uut (
.in1(in1),      //register connect to input
.in2(in2),      //register connect to input
.out(out)       //wire connect to output
);
    initial begin 
    in1=1 ; in2=2 ; //test values assigned to regs
    $display("%d",out) ;
    $finish ;
    end

endmodule

In testbench values can be assigned only to register, ie reg . So input to the adder modules must be connected to registers.

The output is taken from the module using wire , so out port is connected to a wire type. Please go through the comments.

In the initial-end block, initially test values are assigned to inputs. The adder module process data and sum is placed in out port.

The $display command displays the data, in the given example if the output is 3 we could say that adder is working fine.

The $finish system task finishes the simulation.


It is clear that the output changes as the input changes, the only delay preset will be the propagation delay which is not diplayed. This is a combinational circuit as no clock is present in the module.