fpgaNasic
Saturday, May 5, 2018
Error Installing Modelsim Started Edition (could not find ./../linux_rh60/vsim)
›
Installing modelsim Intel FPGA starter edition in Ubuntu 16.04 had some problems. When starting vsim, error message was returned as ...
Sunday, January 26, 2014
PSNR of two gray scale images in Matlab
›
This post is about finding the PSNR of two greyscale images in matlab. The program will show the two images and will display ...
Thursday, July 4, 2013
Verilog Datatypes: Wires,regs and ports
›
Wires Wires aka nets are used to interconnect modules. They can be 1 bit or wider. Wire having more than one bit is called ve...
Tuesday, July 2, 2013
Equality operators in Verilog
›
These operators are used to check the equivalence, greater than or less than. But two additional operators are here which may seem ...
Concatenation operator in Verilog
›
Concatenation operator is used to make a larger operand from smaller operands or to split a large operand into smaller ones. It is ...
Monday, July 1, 2013
Ternary operator in Verilog
›
Ternary operator is used to check "if then else" condition in Verilog. It has three operands. ...
Reduction operators in Verilog
›
Reduction operators are unary operators as they work on a single operand. They work with a multiple-bit operand and reduce them to ...
›
Home
View web version
