Icarus Verilog is a free and opensource Verilog simulation and synthesis tool.
It compiles the verilog source file to some target format known as vvp.
This intermediate format is simulated with vvp command. For synthesis
netlists can be generated.
The verilog designs can be simulated as follows. Here I am going to simulate a simple helloword module.
$ iverilog -o hello hello.v
produce an intermediate format for simulation
$ vvp hello
gives the result
I hope you have a installed modelsim software with its binaries added to the path.
If I am wrong then follow this tutorial.
Here I am proceeding with linux os, of course I will be covering windows too. In both
case things are same but is done in different way.
Create a directory to mess up with
$ mkdir test
Now make a local copy of modelsim.ini file. Your preferences and lib paths are stored in this file.
$ cp /install/altera/12.1/modelsim_ase/modelsim.ini .
Its time to make a work library, all module are compiled to that library before simulation
$ vlib work
This work library must be pointed in the modelsim.ini file. It can be done as follows
$ vmap work work
Verilog file are compiled with vlog command. I am going to compile the
helloworld
module.
$ vlog hello.v
The erros will be displayed in the terminal and if error free simulate it.
$ vsim -c hello -do "run -a" //simulate in commandline
$ vsim hello -do "run -a" //simulate with gui
Here
vsim
starts the simulation and
run -a
runs the simulation.
