Simulating verilog designs with Icarus in Ubuntu

Icarus Verilog is a free and opensource Verilog simulation and synthesis tool. It compiles the verilog source file to some target format known as vvp.

This intermediate format is simulated with vvp command. For synthesis netlists can be generated.

The verilog designs can be simulated as follows. Here I am going to simulate a simple helloword module.

$ iverilog -o hello hello.v   produce an intermediate format for simulation

$ vvp hello                   gives the result