Error Installing Modelsim Started Edition (could not find ./../linux_rh60/vsim)

Installing modelsim Intel FPGA starter edition in Ubuntu 16.04 had some problems.

When starting vsim, error message was returned as
"could not find ./../linux_rh60/vsim"

The problem was solved afer replacing line "
vco="linux_rh60" with vco="linux"

Three libraries where missing, actually there 32 bit versions
 
error while loading shared libraries: libX11.so.6
error while loading shared libraries: libXext.so.6
error while loading shared libraries: libXft.so.2

After installing those libraries by following command vsim started without errors

sudo apt install libxft2:i386
sudo apt install libxext6:i386
sudo apt-get install libx11-6:i386

PSNR of two gray scale images in Matlab

This post is about finding the PSNR of two greyscale images in matlab. The program will show the two images and will display result in an alert box.

inImage = imread('rose_in.bmp');
[rows columns] = size(inImage) ;
subplot(2, 2, 1) ;
imshow(inImage, []);
title('Input image');
set(gcf, 'Position', get(0,'Screensize'));

outImage = imread('rose_out.bmp') ;
[rowsO columnO] = size(outImage) ;
subplot(2, 2, 2);
imshow(outImage, []);
title('Output Image');


squaredErrorImage = (double(inImage) - double(outImage)) .^ 2;
%subplot(2, 2, 3);
%imshow(squaredErrorImage, []);
%title('Squared Error Image');

mse = sum(sum(squaredErrorImage)) / (rows * columns);

PSNR = 10 * log10( 256^2 / mse);

message = sprintf('The mean square error is %.2f.\nThe PSNR = %.2f', mse, PSNR);
msgbox(message);

Verilog Datatypes: Wires,regs and ports

Wires

Wires aka nets are used to interconnect modules. They can be 1 bit or wider. Wire having more than one bit is called vector or bus. On other hand the wires carry output of one module to the input of other module. See how modules are interconnected here.

wire [7:0] test_wire ;

The above statement declares a wire named test_wire with a width of 8 bit.

Regs

Regs are used in procedural statements. In procedural statements the output is assigned to Regs. The reg types can be either sequential or combinational. It can be single bit or vector type. Procedural statements are those statements which appear inside the always block

reg [7:0] test_reg ;

The declaration of a 8 bit reg named test_reg is as above.

Ports

Inside a module the results or data is available on either Wires or Regs. Procedural statements keep the data in regs and assignment statements keep the values in wires. This data are tapped outside the module through ports, exactly output ports. Likewise input to a module is passed through port known as input port.

input  [7:0] test_input ,
output [7:0] test_output ,
output reg [7:0] test_output_reg ,

The first one is a input port. The second one is output port of wire type and the last one is output port of reg type.

Equality operators in Verilog

These operators are used to check the equivalence, greater than or less than. But two additional operators are here which may seem unfamiliar.

Operator	Description
==	Equivalence
===	Literal equivalence
!=	Inequivaity
!==	Literal inequivaity
<	Less than
>	Greater than
≤	Less than or equal to
≥	Greater than or equal to

The following sample code and outputs demonstrates the operators.

module equality_operator ;
    initial begin 
        $display("%b",1'bz==1'bx) ;
        $display("%b",1'bz===1'bx) ;
        $finish ;
    end
endmodule 

$ x
$ 0

Here I am only pointing out the difference between the equivalence operator and the Literal equivalence operator. While comparing two values we expect either a logical one or zero. But in simulation both unknowns(X) and high impedence(Z) values are present.
To get either logical one or zero we should use Literal equivalence operator in simulation, otherwise the output may be X or Z.
But in case of hardware, code for synthesis, we can use equivalence operator, beacause hardware has either logical one or zero.

Concatenation operator in Verilog

Concatenation operator is used to make a larger operand from smaller operands or to split a large operand into smaller ones. It is illegal to use unsized numbers inside the concatenation operator.

The following sample code and outputs demonstrates the operators.

module concatenation_operator ;
    reg [1:0] a ;
    reg [1:0] b ;
    reg [3:0] c ;
    initial begin 
        c = {2'b10,2'b11} ;
        $display("c={2'b10,2'b11}=%b",{2'b10,2'b11}) ;
        {a,b} = c ;
        $display("a = %b \nb = %b",a,b) ;
        $finish ;
    end
endmodule 

$ c={2'b10,2'b11}=1011
$ a = 10
$ b = 11

Two 2-bit numbers are concatenated to form a 4-bit number and is assigned to a 4-bit register c. Now the larger register c is split into two 2-bit values and are assigned to two 2-bit register a and b.

Ternary operator in Verilog

Ternary operator is used to check "if then else"condition in Verilog. It has three operands.

w = x ? y : z ;

The format of Ternary operator is as shown above. If x is one then y is assigned to w and else z is assigned. Ternary operator can be nested to make multi level if statements.
The following sample code and outputs demonstrates the operators.

module ternary_operators ;
    reg [1:0] a,b,c ;
    reg d ;
    initial begin 
        a = 0 ;
        b = 1 ;
        c = 2 ;
        d = 1 ;
        a = d ? b : c ;
        $display(" a = %d",a) ;
        $finish ;
    end
endmodule 

$ a = 1

In the above example value is assigned to a with a ternary_operator. Here the value of d is checked initially which is found to be 1. Hence a is assigned with the value of d which is 1. If d were 0 then a should have been 2. It simply work as a 2X1 Mux.

Reduction operators in Verilog

Reduction operators are unary operators as they work on a single operand. They work with a multiple-bit operand and reduce them to single bit. The operation performed depends on the type of reduction operator.

Operator	Description
&	Reduction AND
|	Reduction OR
^	Reduction XOR
~&	Reduction NAND
~|	Reduction NOR
~^	Reduction XNOR

The following sample code and outputs demonstrates the operators.

module reduction_operators ;
    initial begin 
        $display(" &3'b101 = %b",&3'b101) ;
        $display(" |3'b101 = %b",|3'b101) ;
        $display(" ^3'b101 = %b",^3'b101) ;
        $finish ;
    end
endmodule 

$ &3'b101 = 0
$ |3'b101 = 1
$ ^3'b101 = 0

The reduction & operator performs ANDing of all bits of the operand. The last three operators in the table performs negation of the result produced by the reduction operator.