Equality operators in Verilog

These operators are used to check the equivalence, greater than or less than. But two additional operators are here which may seem unfamiliar.

Operator	Description
==	Equivalence
===	Literal equivalence
!=	Inequivaity
!==	Literal inequivaity
<	Less than
>	Greater than
≤	Less than or equal to
≥	Greater than or equal to

The following sample code and outputs demonstrates the operators.

module equality_operator ;
    initial begin 
        $display("%b",1'bz==1'bx) ;
        $display("%b",1'bz===1'bx) ;
        $finish ;
    end
endmodule 

$ x
$ 0

Here I am only pointing out the difference between the equivalence operator and the Literal equivalence operator. While comparing two values we expect either a logical one or zero. But in simulation both unknowns(X) and high impedence(Z) values are present.
To get either logical one or zero we should use Literal equivalence operator in simulation, otherwise the output may be X or Z.
But in case of hardware, code for synthesis, we can use equivalence operator, beacause hardware has either logical one or zero.