Ternary operator in Verilog

Ternary operator is used to check "if then else"condition in Verilog. It has three operands.

w = x ? y : z ;

The format of Ternary operator is as shown above. If x is one then y is assigned to w and else z is assigned. Ternary operator can be nested to make multi level if statements.
The following sample code and outputs demonstrates the operators.

module ternary_operators ;
    reg [1:0] a,b,c ;
    reg d ;
    initial begin 
        a = 0 ;
        b = 1 ;
        c = 2 ;
        d = 1 ;
        a = d ? b : c ;
        $display(" a = %d",a) ;
        $finish ;
    end
endmodule 

$ a = 1

In the above example value is assigned to a with a ternary_operator. Here the value of d is checked initially which is found to be 1. Hence a is assigned with the value of d which is 1. If d were 0 then a should have been 2. It simply work as a 2X1 Mux.