Reduction operators in Verilog

Reduction operators are unary operators as they work on a single operand. They work with a multiple-bit operand and reduce them to single bit. The operation performed depends on the type of reduction operator.

Operator	Description
&	Reduction AND
|	Reduction OR
^	Reduction XOR
~&	Reduction NAND
~|	Reduction NOR
~^	Reduction XNOR

The following sample code and outputs demonstrates the operators.

module reduction_operators ;
    initial begin 
        $display(" &3'b101 = %b",&3'b101) ;
        $display(" |3'b101 = %b",|3'b101) ;
        $display(" ^3'b101 = %b",^3'b101) ;
        $finish ;
    end
endmodule 

$ &3'b101 = 0
$ |3'b101 = 1
$ ^3'b101 = 0

The reduction & operator performs ANDing of all bits of the operand. The last three operators in the table performs negation of the result produced by the reduction operator.