Concatenation operator in Verilog

Concatenation operator is used to make a larger operand from smaller operands or to split a large operand into smaller ones. It is illegal to use unsized numbers inside the concatenation operator.

The following sample code and outputs demonstrates the operators.

module concatenation_operator ;
    reg [1:0] a ;
    reg [1:0] b ;
    reg [3:0] c ;
    initial begin 
        c = {2'b10,2'b11} ;
        $display("c={2'b10,2'b11}=%b",{2'b10,2'b11}) ;
        {a,b} = c ;
        $display("a = %b \nb = %b",a,b) ;
        $finish ;
    end
endmodule 

$ c={2'b10,2'b11}=1011
$ a = 10
$ b = 11

Two 2-bit numbers are concatenated to form a 4-bit number and is assigned to a 4-bit register c. Now the larger register c is split into two 2-bit values and are assigned to two 2-bit register a and b.