Timescale in Verilog

Usually in testbenches we need to put some delay for testing the module under test. The `timescale directive controls the unit used to specify the time and the precision of it. The syntax is given below.
  

`timescale time_unit/time_precision

It can be explained with an example.

`timescale 1ns/1ps
module timescale ;
reg clk ;
    initial begin
        $timeformat(-9,2,"ns", 10);
                    $display("time : %t",$time) ;
        #10         $display("time : %t",$time) ;
        #1          $display("time : %t",$time) ;
        $finish ;

    end
endmodule

A delay is put with a preceeding #. In the given example the time_unit is 1ns and the precision is 1ps .
The first $display will print at time zero as no delay is introduced. Now a delay of #10 is introduced. The timescale says the time_unit is in 1ns and hence 10x1ns = 10ns delay is put there.
Now time_precision tells the how precise the time is, ie the minimum delay that can be given or the minimum time fraction that can be observed in the simulator.
In the above example it is possible to monitor the waveform with a resolution of 1ps and the minimum time for which an event can be delayed is 1ps. The output is given below.

$ time : 0.00ns
$ time : 10.00ns
$ time : 11.00ns

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