My first synthesizable verilog module (sequential)

I think you may have gone through my first combinational module here. Now I am introducing you to my first sequential module, of course an adder, but now its sequntial.
You will find the difference between them as you go ahead.

Here is a simple sequential adder module

module adder (
input clock ,
input reset ,
input [7:0] in1, //input one 8 bit width
input [7:0] in2, //input two
output reg [8:0] out //output sum 9bit
);

always @ (posedge clock) begin 
    if(reset) begin
        out <= 0 ;
    end
    else begin
        out <= in1 + in2 ;
    end
end 

endmodule

It differs from the combinational adder circuit due to the presence of clock input. Here everything is synchonised to the clock, ie the input data is sampled and added with reference to the clock. The addition may occur in rising edge or falling edge.

In this adder, the block of statements inside the always block is executed at every positive edge or rising edge of clock. Inside the block it checks for reset signal and makes the out zero if the reset is high. If the reset is low then the sum is placed at out

One thing we shoule keep in mind that, if we place the data in the current cycle the output will be available after next rising edge. One clock cycle delay is preset in processing.

`timescale 1ns/1ns 
module adder_test ;

reg clock ;
reg reset ;
reg [7:0] in1 ; //declaration of register in1
reg [7:0] in2 ; //declaration of register in2
wire [8:0] out ; //declaration of wire out

adder adder_uut (
.clock(clock),      
.reset(reset),     
.in1(in1),      //register connect to input
.in2(in2),      //register connect to input
.out(out)       //wire connect to output
);
    initial begin 
    clock = 0 ;
    reset = 1 ;
    in1=1 ; in2=2 ; //test values assigned to regs
    #8 ;
    reset = 0 ;
    #4 ;
    $display("%d",out) ;
    $finish ;
    end

always #2 clock = ~clock ;

endmodule

Leave the timescale for a while and only be aware that all time units are in nanoseconds.

The #8 is not a hashtag, it put a delay of 8ns. Intially the adder is resetted by making reset high. After 8ns the reset is deasserted. Oh, I forgot mention about the clock.

The main challenge here is clock. We need to supply clock to the adder module. The always block makes a clock of 4ns period. The statement instructs to toggle the clock signal with a delay 2ns which produce a 4ns clock.

From the waveform it is clear that the output changes only at the rising edge of clock eventhough inputs are present from the start. A 4ns delay is introduced before the display command to ensure that the process is over and result is ready.


This is the difference between combinational and sequential modules.