Replication operator in Verilog

Replication operator is used to replicate a group of bits n times. The same number, it may be a wire, register or a number , can be repeated several times. The syntax is given below.

{n{bit_pattern}}

Some examples are given below

module replication ;
reg [1:0] reg1 ;
    initial begin 
        reg1 = 2'b10 ;
        $display(" {2{2'b10}} %b",{2{2'b10}}) ;
        $display(" reg1       %b",reg1) ;
        $display(" {2{reg1}}  %b",{2{reg1}}) ;
        $finish ;
    end
endmodule 

Output is as follows

$ {2{2'b10}} 1010
$ reg1 10
$ {2{reg1}} 1010

In first $display the bit pattern 2'b10 is replicated twice and in third one the content of register reg1 is replicated twice.