Arithmetic operators in Verilog

This post is about Verilog Arithmetic operators.

Operator	Description
+	Addition
-	Subtraction
*	Multiplication
/	Division
%	Modulus
**	Power

The following sample code and outputs demonstrates the arithmetic operators.

module arithmetic ;
reg [1:0] a ;
reg [1:0] b ;
reg [1:0] result ;

    initial begin 
        a = 2'd3 ;
        b = 2'd2 ; 
        result = a + b ;
        $display("a + b  = %b",result) ;
        result = b - a ;
        $display("b - a  = %b",result) ;
        $display("2 * 3  = %5b",2*3) ;
        $display("3 / 2  = %5b",3/2) ;
        $display("3 %s 2 = %5b","%",3%2) ;
        $display("3 ** 2 = %5d",3**2) ;
        $finish ;
    end
endmodule 

$ a + b = 01
$ b - a = 11
$ 2 * 3 = 00110
$ 3 / 2 = 00001
$ 3 % 2 = 00001
$ 3 **2 = 9

In the example of addition operator two numbers are added and the output is assigned to a 2 bit register. But verilog is not capable of handling overflow itself and the result is 01 instead of 101.
The tricky part in subraction is that the negetive number is represented in 2's complement format. That why -1 appears as 11.
Division gives the results as integers, ie, no fractional part is present.
Modulus operator gives the remainder of Division.
And the last one is the raise to operator.