Negation operators in Verilog

They are unary operators and are of two types, bitwise negation and logical negation.
Bitwise negation gives the complement of number as each bit is complemented.
I have mentioned in my earlier post that logical operators consider all non zero operands as logical one and others as zero. This single bit result is then complemented with a logical negation operator.

Operator	Description
~	Bitwise negation
!	Logical negation

The following sample code and outputs demonstrates the operators.

module negation_operator ;
    initial begin 
        $display(" ~3'b101 = %b",~3'b101) ;
        $display(" !1'b0   = %b",!1'b0) ;
        $display(" !2'b10  = %b",!2'b10) ;
        $finish ;
    end
endmodule 

$ ~3'b101 = 013
$ !1'b0 = 1
$ !2'b10 = 0

Its posiible to say that the Bitwise negation gives the 1's complement of a number. It toggles every bit of the operand.

Logical operators in Verilog

This post is about Logical operators in Verilog. They are used to evaluate true or false condition in statement. The result of these statement will be either 1 or 0.

Operator	Description
&&	Logical AND
||	Logical OR

The following sample code and outputs demonstrates the operators.

module logical_operators ;
    initial begin 
        $display("2'b00 && 2'b11 = %b",2'b00 && 2'b11) ;
        $display("2'b11 && 2'b11 = %b",2'b11 && 2'b11) ;
        $display("2'b00 || 2'b11 = %b",2'b00 || 2'b11) ;
        $display("2'b11 || 2'b11 = %b",2'b11 || 2'b11) ;
        $finish ;
    end
endmodule 

$ 2'b00 && 2'b11 = 0
$ 2'b11 && 2'b11 = 1
$ 2'b00 || 2'b11 = 1
$ 2'b11 || 2'b11 = 1

It is clear from the example that the operator considers the multibit non zero values as logical 1 and others as zero. Then it just performs logical AND or OR operation on the operands.

Bitwise operators and Shift operators in Verilog

This post is about Verilog Bitwise operators. They include both logical operators and shift operators..

Operator	Description
|	OR
&	AND
^	Exclusive OR
<<	Shift left
>>	Shift right

The following sample code and outputs demonstrates the operators.

module bitwise_operators ;
    initial begin 
        $display(" 2'b11|2'b10  = %b",2'b11|2'b10) ;
        $display(" 2'b11&2'b10  = %b",2'b11&2'b10) ;
        $display(" 2'b11^2'b10  = %b",2'b11^2'b10) ;
        $display(" 3'b101<<1    = %b",3'b101<<1) ;
        $display(" 3'b101>>1    = %b",3'b101>>1) ;
        $finish ;
    end
endmodule 

$ 2'b11|2'b10 = 11
$ 2'b11&2'b10 = 10
$ 2'b11^2'b10 = 01
$ 3'b101<<1 = 010
$ 3'b101>>1 = 010

Bitwise operators work on two operands of same size(bit width) and the result is of same size. Here logical operations are performed on the corresponding bits of each operands. The syntax of left shift operator is given below

  number << n

The number is shifted left n times and the new positions are filled with zeros.

Arithmetic operators in Verilog

This post is about Verilog Arithmetic operators.

Operator	Description
+	Addition
-	Subtraction
*	Multiplication
/	Division
%	Modulus
**	Power

The following sample code and outputs demonstrates the arithmetic operators.

module arithmetic ;
reg [1:0] a ;
reg [1:0] b ;
reg [1:0] result ;

    initial begin 
        a = 2'd3 ;
        b = 2'd2 ; 
        result = a + b ;
        $display("a + b  = %b",result) ;
        result = b - a ;
        $display("b - a  = %b",result) ;
        $display("2 * 3  = %5b",2*3) ;
        $display("3 / 2  = %5b",3/2) ;
        $display("3 %s 2 = %5b","%",3%2) ;
        $display("3 ** 2 = %5d",3**2) ;
        $finish ;
    end
endmodule 

$ a + b = 01
$ b - a = 11
$ 2 * 3 = 00110
$ 3 / 2 = 00001
$ 3 % 2 = 00001
$ 3 **2 = 9

In the example of addition operator two numbers are added and the output is assigned to a 2 bit register. But verilog is not capable of handling overflow itself and the result is 01 instead of 101.
The tricky part in subraction is that the negetive number is represented in 2's complement format. That why -1 appears as 11.
Division gives the results as integers, ie, no fractional part is present.
Modulus operator gives the remainder of Division.
And the last one is the raise to operator.

Replication operator in Verilog

Replication operator is used to replicate a group of bits n times. The same number, it may be a wire, register or a number , can be repeated several times. The syntax is given below.

{n{bit_pattern}}

Some examples are given below

module replication ;
reg [1:0] reg1 ;
    initial begin 
        reg1 = 2'b10 ;
        $display(" {2{2'b10}} %b",{2{2'b10}}) ;
        $display(" reg1       %b",reg1) ;
        $display(" {2{reg1}}  %b",{2{reg1}}) ;
        $finish ;
    end
endmodule 

Output is as follows

$ {2{2'b10}} 1010
$ reg1 10
$ {2{reg1}} 1010

In first $display the bit pattern 2'b10 is replicated twice and in third one the content of register reg1 is replicated twice.

Timescale in Verilog

Usually in testbenches we need to put some delay for testing the module under test. The `timescale directive controls the unit used to specify the time and the precision of it. The syntax is given below.
  

`timescale time_unit/time_precision

It can be explained with an example.

`timescale 1ns/1ps
module timescale ;
reg clk ;
    initial begin
        $timeformat(-9,2,"ns", 10);
                    $display("time : %t",$time) ;
        #10         $display("time : %t",$time) ;
        #1          $display("time : %t",$time) ;
        $finish ;

    end
endmodule

A delay is put with a preceeding #. In the given example the time_unit is 1ns and the precision is 1ps .
The first $display will print at time zero as no delay is introduced. Now a delay of #10 is introduced. The timescale says the time_unit is in 1ns and hence 10x1ns = 10ns delay is put there.
Now time_precision tells the how precise the time is, ie the minimum delay that can be given or the minimum time fraction that can be observed in the simulator.
In the above example it is possible to monitor the waveform with a resolution of 1ps and the minimum time for which an event can be delayed is 1ps. The output is given below.

$ time : 0.00ns
$ time : 10.00ns
$ time : 11.00ns

More info

What is a module in verilog

The main building block in Verilog is the module. The circuits are build by connecting modules together.
Simply speaking, a module can be considered as an IC. Please have a look at this simple adder module which can be considered as an adder IC. It takes some data and produce output. Here, in case of adder, the output is sum.

Communicating with the outside world

Modules use ports to communicate with the outside world.
The data is passed to the module through input port. The port can be a single bit line or a bit vector.

The output of the modules are present in output port. This port can be a single bit or a bit vector.
There are inout ports which are capable of communicating in both directions.

The funtionality of a large circuit is divided into modules. Then each modules are designed and tested. Finally these modules are interconnected to make the final circuit. Different modules are interconnected with wires.