Logical operators in Verilog

This post is about Logical operators in Verilog. They are used to evaluate true or false condition in statement. The result of these statement will be either 1 or 0.

Operator	Description
&&	Logical AND
||	Logical OR

The following sample code and outputs demonstrates the operators.

module logical_operators ;
    initial begin 
        $display("2'b00 && 2'b11 = %b",2'b00 && 2'b11) ;
        $display("2'b11 && 2'b11 = %b",2'b11 && 2'b11) ;
        $display("2'b00 || 2'b11 = %b",2'b00 || 2'b11) ;
        $display("2'b11 || 2'b11 = %b",2'b11 || 2'b11) ;
        $finish ;
    end
endmodule 

$ 2'b00 && 2'b11 = 0
$ 2'b11 && 2'b11 = 1
$ 2'b00 || 2'b11 = 1
$ 2'b11 || 2'b11 = 1

It is clear from the example that the operator considers the multibit non zero values as logical 1 and others as zero. Then it just performs logical AND or OR operation on the operands.