Bitwise operators and Shift operators in Verilog

This post is about Verilog Bitwise operators. They include both logical operators and shift operators..

Operator	Description
|	OR
&	AND
^	Exclusive OR
<<	Shift left
>>	Shift right

The following sample code and outputs demonstrates the operators.

module bitwise_operators ;
    initial begin 
        $display(" 2'b11|2'b10  = %b",2'b11|2'b10) ;
        $display(" 2'b11&2'b10  = %b",2'b11&2'b10) ;
        $display(" 2'b11^2'b10  = %b",2'b11^2'b10) ;
        $display(" 3'b101<<1    = %b",3'b101<<1) ;
        $display(" 3'b101>>1    = %b",3'b101>>1) ;
        $finish ;
    end
endmodule 

$ 2'b11|2'b10 = 11
$ 2'b11&2'b10 = 10
$ 2'b11^2'b10 = 01
$ 3'b101<<1 = 010
$ 3'b101>>1 = 010

Bitwise operators work on two operands of same size(bit width) and the result is of same size. Here logical operations are performed on the corresponding bits of each operands. The syntax of left shift operator is given below

  number << n

The number is shifted left n times and the new positions are filled with zeros.