Negation operators in Verilog

They are unary operators and are of two types, bitwise negation and logical negation.
Bitwise negation gives the complement of number as each bit is complemented.
I have mentioned in my earlier post that logical operators consider all non zero operands as logical one and others as zero. This single bit result is then complemented with a logical negation operator.

Operator	Description
~	Bitwise negation
!	Logical negation

The following sample code and outputs demonstrates the operators.

module negation_operator ;
    initial begin 
        $display(" ~3'b101 = %b",~3'b101) ;
        $display(" !1'b0   = %b",!1'b0) ;
        $display(" !2'b10  = %b",!2'b10) ;
        $finish ;
    end
endmodule 

$ ~3'b101 = 013
$ !1'b0 = 1
$ !2'b10 = 0

Its posiible to say that the Bitwise negation gives the 1's complement of a number. It toggles every bit of the operand.