Verilog Datatypes: Wires,regs and ports

Wires

Wires aka nets are used to interconnect modules. They can be 1 bit or wider. Wire having more than one bit is called vector or bus. On other hand the wires carry output of one module to the input of other module. See how modules are interconnected here.

wire [7:0] test_wire ;

The above statement declares a wire named test_wire with a width of 8 bit.

Regs

Regs are used in procedural statements. In procedural statements the output is assigned to Regs. The reg types can be either sequential or combinational. It can be single bit or vector type. Procedural statements are those statements which appear inside the always block

reg [7:0] test_reg ;

The declaration of a 8 bit reg named test_reg is as above.

Ports

Inside a module the results or data is available on either Wires or Regs. Procedural statements keep the data in regs and assignment statements keep the values in wires. This data are tapped outside the module through ports, exactly output ports. Likewise input to a module is passed through port known as input port.

input  [7:0] test_input ,
output [7:0] test_output ,
output reg [7:0] test_output_reg ,

The first one is a input port. The second one is output port of wire type and the last one is output port of reg type.

Equality operators in Verilog

These operators are used to check the equivalence, greater than or less than. But two additional operators are here which may seem unfamiliar.

Operator	Description
==	Equivalence
===	Literal equivalence
!=	Inequivaity
!==	Literal inequivaity
<	Less than
>	Greater than
≤	Less than or equal to
≥	Greater than or equal to

The following sample code and outputs demonstrates the operators.

module equality_operator ;
    initial begin 
        $display("%b",1'bz==1'bx) ;
        $display("%b",1'bz===1'bx) ;
        $finish ;
    end
endmodule 

$ x
$ 0

Here I am only pointing out the difference between the equivalence operator and the Literal equivalence operator. While comparing two values we expect either a logical one or zero. But in simulation both unknowns(X) and high impedence(Z) values are present.
To get either logical one or zero we should use Literal equivalence operator in simulation, otherwise the output may be X or Z.
But in case of hardware, code for synthesis, we can use equivalence operator, beacause hardware has either logical one or zero.

Concatenation operator in Verilog

Concatenation operator is used to make a larger operand from smaller operands or to split a large operand into smaller ones. It is illegal to use unsized numbers inside the concatenation operator.

The following sample code and outputs demonstrates the operators.

module concatenation_operator ;
    reg [1:0] a ;
    reg [1:0] b ;
    reg [3:0] c ;
    initial begin 
        c = {2'b10,2'b11} ;
        $display("c={2'b10,2'b11}=%b",{2'b10,2'b11}) ;
        {a,b} = c ;
        $display("a = %b \nb = %b",a,b) ;
        $finish ;
    end
endmodule 

$ c={2'b10,2'b11}=1011
$ a = 10
$ b = 11

Two 2-bit numbers are concatenated to form a 4-bit number and is assigned to a 4-bit register c. Now the larger register c is split into two 2-bit values and are assigned to two 2-bit register a and b.

Ternary operator in Verilog

Ternary operator is used to check "if then else"condition in Verilog. It has three operands.

w = x ? y : z ;

The format of Ternary operator is as shown above. If x is one then y is assigned to w and else z is assigned. Ternary operator can be nested to make multi level if statements.
The following sample code and outputs demonstrates the operators.

module ternary_operators ;
    reg [1:0] a,b,c ;
    reg d ;
    initial begin 
        a = 0 ;
        b = 1 ;
        c = 2 ;
        d = 1 ;
        a = d ? b : c ;
        $display(" a = %d",a) ;
        $finish ;
    end
endmodule 

$ a = 1

In the above example value is assigned to a with a ternary_operator. Here the value of d is checked initially which is found to be 1. Hence a is assigned with the value of d which is 1. If d were 0 then a should have been 2. It simply work as a 2X1 Mux.

Reduction operators in Verilog

Reduction operators are unary operators as they work on a single operand. They work with a multiple-bit operand and reduce them to single bit. The operation performed depends on the type of reduction operator.

Operator	Description
&	Reduction AND
|	Reduction OR
^	Reduction XOR
~&	Reduction NAND
~|	Reduction NOR
~^	Reduction XNOR

The following sample code and outputs demonstrates the operators.

module reduction_operators ;
    initial begin 
        $display(" &3'b101 = %b",&3'b101) ;
        $display(" |3'b101 = %b",|3'b101) ;
        $display(" ^3'b101 = %b",^3'b101) ;
        $finish ;
    end
endmodule 

$ &3'b101 = 0
$ |3'b101 = 1
$ ^3'b101 = 0

The reduction & operator performs ANDing of all bits of the operand. The last three operators in the table performs negation of the result produced by the reduction operator.

Negation operators in Verilog

They are unary operators and are of two types, bitwise negation and logical negation.
Bitwise negation gives the complement of number as each bit is complemented.
I have mentioned in my earlier post that logical operators consider all non zero operands as logical one and others as zero. This single bit result is then complemented with a logical negation operator.

Operator	Description
~	Bitwise negation
!	Logical negation

The following sample code and outputs demonstrates the operators.

module negation_operator ;
    initial begin 
        $display(" ~3'b101 = %b",~3'b101) ;
        $display(" !1'b0   = %b",!1'b0) ;
        $display(" !2'b10  = %b",!2'b10) ;
        $finish ;
    end
endmodule 

$ ~3'b101 = 013
$ !1'b0 = 1
$ !2'b10 = 0

Its posiible to say that the Bitwise negation gives the 1's complement of a number. It toggles every bit of the operand.

Logical operators in Verilog

This post is about Logical operators in Verilog. They are used to evaluate true or false condition in statement. The result of these statement will be either 1 or 0.

Operator	Description
&&	Logical AND
||	Logical OR

The following sample code and outputs demonstrates the operators.

module logical_operators ;
    initial begin 
        $display("2'b00 && 2'b11 = %b",2'b00 && 2'b11) ;
        $display("2'b11 && 2'b11 = %b",2'b11 && 2'b11) ;
        $display("2'b00 || 2'b11 = %b",2'b00 || 2'b11) ;
        $display("2'b11 || 2'b11 = %b",2'b11 || 2'b11) ;
        $finish ;
    end
endmodule 

$ 2'b00 && 2'b11 = 0
$ 2'b11 && 2'b11 = 1
$ 2'b00 || 2'b11 = 1
$ 2'b11 || 2'b11 = 1

It is clear from the example that the operator considers the multibit non zero values as logical 1 and others as zero. Then it just performs logical AND or OR operation on the operands.

Bitwise operators and Shift operators in Verilog

This post is about Verilog Bitwise operators. They include both logical operators and shift operators..

Operator	Description
|	OR
&	AND
^	Exclusive OR
<<	Shift left
>>	Shift right

The following sample code and outputs demonstrates the operators.

module bitwise_operators ;
    initial begin 
        $display(" 2'b11|2'b10  = %b",2'b11|2'b10) ;
        $display(" 2'b11&2'b10  = %b",2'b11&2'b10) ;
        $display(" 2'b11^2'b10  = %b",2'b11^2'b10) ;
        $display(" 3'b101<<1    = %b",3'b101<<1) ;
        $display(" 3'b101>>1    = %b",3'b101>>1) ;
        $finish ;
    end
endmodule 

$ 2'b11|2'b10 = 11
$ 2'b11&2'b10 = 10
$ 2'b11^2'b10 = 01
$ 3'b101<<1 = 010
$ 3'b101>>1 = 010

Bitwise operators work on two operands of same size(bit width) and the result is of same size. Here logical operations are performed on the corresponding bits of each operands. The syntax of left shift operator is given below

  number << n

The number is shifted left n times and the new positions are filled with zeros.

Arithmetic operators in Verilog

This post is about Verilog Arithmetic operators.

Operator	Description
+	Addition
-	Subtraction
*	Multiplication
/	Division
%	Modulus
**	Power

The following sample code and outputs demonstrates the arithmetic operators.

module arithmetic ;
reg [1:0] a ;
reg [1:0] b ;
reg [1:0] result ;

    initial begin 
        a = 2'd3 ;
        b = 2'd2 ; 
        result = a + b ;
        $display("a + b  = %b",result) ;
        result = b - a ;
        $display("b - a  = %b",result) ;
        $display("2 * 3  = %5b",2*3) ;
        $display("3 / 2  = %5b",3/2) ;
        $display("3 %s 2 = %5b","%",3%2) ;
        $display("3 ** 2 = %5d",3**2) ;
        $finish ;
    end
endmodule 

$ a + b = 01
$ b - a = 11
$ 2 * 3 = 00110
$ 3 / 2 = 00001
$ 3 % 2 = 00001
$ 3 **2 = 9

In the example of addition operator two numbers are added and the output is assigned to a 2 bit register. But verilog is not capable of handling overflow itself and the result is 01 instead of 101.
The tricky part in subraction is that the negetive number is represented in 2's complement format. That why -1 appears as 11.
Division gives the results as integers, ie, no fractional part is present.
Modulus operator gives the remainder of Division.
And the last one is the raise to operator.

Replication operator in Verilog

Replication operator is used to replicate a group of bits n times. The same number, it may be a wire, register or a number , can be repeated several times. The syntax is given below.

{n{bit_pattern}}

Some examples are given below

module replication ;
reg [1:0] reg1 ;
    initial begin 
        reg1 = 2'b10 ;
        $display(" {2{2'b10}} %b",{2{2'b10}}) ;
        $display(" reg1       %b",reg1) ;
        $display(" {2{reg1}}  %b",{2{reg1}}) ;
        $finish ;
    end
endmodule 

Output is as follows

$ {2{2'b10}} 1010
$ reg1 10
$ {2{reg1}} 1010

In first $display the bit pattern 2'b10 is replicated twice and in third one the content of register reg1 is replicated twice.

Timescale in Verilog

Usually in testbenches we need to put some delay for testing the module under test. The `timescale directive controls the unit used to specify the time and the precision of it. The syntax is given below.
  

`timescale time_unit/time_precision

It can be explained with an example.

`timescale 1ns/1ps
module timescale ;
reg clk ;
    initial begin
        $timeformat(-9,2,"ns", 10);
                    $display("time : %t",$time) ;
        #10         $display("time : %t",$time) ;
        #1          $display("time : %t",$time) ;
        $finish ;

    end
endmodule

A delay is put with a preceeding #. In the given example the time_unit is 1ns and the precision is 1ps .
The first $display will print at time zero as no delay is introduced. Now a delay of #10 is introduced. The timescale says the time_unit is in 1ns and hence 10x1ns = 10ns delay is put there.
Now time_precision tells the how precise the time is, ie the minimum delay that can be given or the minimum time fraction that can be observed in the simulator.
In the above example it is possible to monitor the waveform with a resolution of 1ps and the minimum time for which an event can be delayed is 1ps. The output is given below.

$ time : 0.00ns
$ time : 10.00ns
$ time : 11.00ns

More info

What is a module in verilog

The main building block in Verilog is the module. The circuits are build by connecting modules together.
Simply speaking, a module can be considered as an IC. Please have a look at this simple adder module which can be considered as an adder IC. It takes some data and produce output. Here, in case of adder, the output is sum.

Communicating with the outside world

Modules use ports to communicate with the outside world.
The data is passed to the module through input port. The port can be a single bit line or a bit vector.

The output of the modules are present in output port. This port can be a single bit or a bit vector.
There are inout ports which are capable of communicating in both directions.

The funtionality of a large circuit is divided into modules. Then each modules are designed and tested. Finally these modules are interconnected to make the final circuit. Different modules are interconnected with wires.

Representing numbers in verilog

The base of the number is a tricky part in verilog. If no base is specified for a number then it is a decimel number,ie it has a base of 10.

As we are dealing with either registers or wires with fixed bit width, the the number of bits must be also specified. If the number of bits is not specified, compiler consider it as 32 bit number, truncation or zero padding can occur.

In general a number can be represented as
   (width)'(base)(number)
  8'b11110000  represents a 8 bit binary number
  8'hFE        represents a 8 bit hexadecimel number
  4'd3         represents a 4 bit decimel number
  3'o7         represents a 3 bit octal number

It is not a strict rule to specify the bit width and base when a number is given. Simulation may pass with some warnings, but some synthesizers may check for it and pop up errors. So better follow this style.

module display ;
    initial begin 
        $display("8'b11110000 is %b",8'b11110000) ;
        $display("8'hFE       is %b",8'hFE) ;
        $display("4'd3        is %b",4'd3) ;
        $display("3'o7        is %b",3'o7) ;
    $finish ;
    end 
endmodule 

The output is given below.

$ 8'b11110000 is 11110000
$ 8'hFE is 11111110
$ 4'd3 is 0011
$ 3'o7 is 111

Assigning numbers

Assigning numbers may lead to truncation or padding. It can be explained with an example.

module assignm ;
reg [1:0] reg1 ;
reg [1:0] reg2 ;
reg [1:0] reg3 ;
    initial begin 
        reg1 = 4 ;
        reg2 = 1 ;
        reg3 = {1'b1,1'b1} ;
        $display("reg1 %b",reg1) ;
        $display("reg2 %b",reg2) ;
        $display("reg2 %b",reg3) ;
    $finish ;
    end 
endmodule 

The output is given below.

$ reg1 00
$ reg2 01
$ reg3 11

Number 4 (binary 100) is assigned to a 2 bit register reg1 and it is clear that the msb bit is truncated and the content of reg1 is displayed as 00.

Number 1 (binary 1) is assigned to a 2 bit register reg2 and a msb bit 0 is added which makes the result 01.

In case of reg3, two single bit numbers are concatenated to form a two bit number and assigned to a two bit resgister. More about concatenation operator is available here

Commenting in verilog

Like other programming languages verilog supports both single-line comment and block comment.

Single line comment starts with // and ends at the end of line.

    ...........
    #4 ;
    $display("%d",out) ; //prints value 
    //$finish ;
    end
    ............

In the above code the parts in green color italics are commented. As you can see its possible to comment single line here

    ............
    initial begin 
    /*clock = 0 ;
    reset = 1 ;*/
    in1=1 ; in2=2 ;
    ............

Now, this is block comment which enables to comment a block of data.

Simulating verilog designs with Icarus in Ubuntu

Icarus Verilog is a free and opensource Verilog simulation and synthesis tool. It compiles the verilog source file to some target format known as vvp.

This intermediate format is simulated with vvp command. For synthesis netlists can be generated.

The verilog designs can be simulated as follows. Here I am going to simulate a simple helloword module.

$ iverilog -o hello hello.v   produce an intermediate format for simulation

$ vvp hello                   gives the result

Installing Icarus/iverilog(free verilog simulator) in Ubuntu

Icarus Verilog is a free and opensource Verilog simulation and synthesis tool. It compiles the verilog source file to some target format known as vvp.

This intermediate format is simulated with vvp command. For synthesis netlists can be generated.

Icarus verilog is now available in Ubuntu respository and can be installed with apt command

$ sudo apt-get install iverilog

My first synthesizable verilog module (sequential)

I think you may have gone through my first combinational module here. Now I am introducing you to my first sequential module, of course an adder, but now its sequntial.
You will find the difference between them as you go ahead.

Here is a simple sequential adder module

module adder (
input clock ,
input reset ,
input [7:0] in1, //input one 8 bit width
input [7:0] in2, //input two
output reg [8:0] out //output sum 9bit
);

always @ (posedge clock) begin 
    if(reset) begin
        out <= 0 ;
    end
    else begin
        out <= in1 + in2 ;
    end
end 

endmodule

It differs from the combinational adder circuit due to the presence of clock input. Here everything is synchonised to the clock, ie the input data is sampled and added with reference to the clock. The addition may occur in rising edge or falling edge.

In this adder, the block of statements inside the always block is executed at every positive edge or rising edge of clock. Inside the block it checks for reset signal and makes the out zero if the reset is high. If the reset is low then the sum is placed at out

One thing we shoule keep in mind that, if we place the data in the current cycle the output will be available after next rising edge. One clock cycle delay is preset in processing.

`timescale 1ns/1ns 
module adder_test ;

reg clock ;
reg reset ;
reg [7:0] in1 ; //declaration of register in1
reg [7:0] in2 ; //declaration of register in2
wire [8:0] out ; //declaration of wire out

adder adder_uut (
.clock(clock),      
.reset(reset),     
.in1(in1),      //register connect to input
.in2(in2),      //register connect to input
.out(out)       //wire connect to output
);
    initial begin 
    clock = 0 ;
    reset = 1 ;
    in1=1 ; in2=2 ; //test values assigned to regs
    #8 ;
    reset = 0 ;
    #4 ;
    $display("%d",out) ;
    $finish ;
    end

always #2 clock = ~clock ;

endmodule

Leave the timescale for a while and only be aware that all time units are in nanoseconds.

The #8 is not a hashtag, it put a delay of 8ns. Intially the adder is resetted by making reset high. After 8ns the reset is deasserted. Oh, I forgot mention about the clock.

The main challenge here is clock. We need to supply clock to the adder module. The always block makes a clock of 4ns period. The statement instructs to toggle the clock signal with a delay 2ns which produce a 4ns clock.

From the waveform it is clear that the output changes only at the rising edge of clock eventhough inputs are present from the start. A 4ns delay is introduced before the display command to ensure that the process is over and result is ready.


This is the difference between combinational and sequential modules.

My first synthesizable verilog module (combinational)

Here I am going to explain about the simulation of a simple synthesizable combinational module. What is synthesizable ? I will tell you in detail later.

Now keep in mind that each and every verilog module cannot be ported to fpga or asic, such as the module having for loop, while loop etc.

A simple adder module is given below.

module adder (
input [7:0] in1, //input one 8 bit width
input [7:0] in2, //input two
output [8:0] out //output sum 9bit
);

assign out = in1 + in2 ; //assigns sum to out

endmodule

A module can be considered as an IC. A module communicates with outside world through ports. Data is passed to the module using input port and the result is available on output port. Here two inputs are present, in1 and in2, having a width of 8 bit. We apply input data to be added on in1 and in2. The sum is available on output port out.

Inorder to check the functionality of the module we need to supply the input and monitor the output right. The perform these functions the module is put inside another module called testbench.

The testbench supplies the data and checks or displays the result.First I will give the testbench and then I will explain.

module adder_test ;

reg [7:0] in1 ; //declaration of register in1
reg [7:0] in2 ; //declaration of register in2
wire [8:0] out ; //declaration of wire out

adder adder_uut (
.in1(in1),      //register connect to input
.in2(in2),      //register connect to input
.out(out)       //wire connect to output
);
    initial begin 
    in1=1 ; in2=2 ; //test values assigned to regs
    $display("%d",out) ;
    $finish ;
    end

endmodule

In testbench values can be assigned only to register, ie reg . So input to the adder modules must be connected to registers.

The output is taken from the module using wire , so out port is connected to a wire type. Please go through the comments.

In the initial-end block, initially test values are assigned to inputs. The adder module process data and sum is placed in out port.

The $display command displays the data, in the given example if the output is 3 we could say that adder is working fine.

The $finish system task finishes the simulation.


It is clear that the output changes as the input changes, the only delay preset will be the propagation delay which is not diplayed. This is a combinational circuit as no clock is present in the module.

Simulating Verilog design with modelsim in Ubuntu

I hope you have a installed modelsim software with its binaries added to the path.
If I am wrong then follow this tutorial.
Here I am proceeding with linux os, of course I will be covering windows too. In both case things are same but is done in different way.

Create a directory to mess up with
$ mkdir test

Now make a local copy of modelsim.ini file. Your preferences and lib paths are stored in this file.
$ cp /install/altera/12.1/modelsim_ase/modelsim.ini .

Its time to make a work library, all module are compiled to that library before simulation
$ vlib work

This work library must be pointed in the modelsim.ini file. It can be done as follows
$ vmap work work

Verilog file are compiled with vlog command. I am going to compile the helloworld module.
$ vlog hello.v

The erros will be displayed in the terminal and if error free simulate it.
$ vsim -c hello -do "run -a" //simulate in commandline
$ vsim hello -do "run -a" //simulate with gui

Here vsim starts the simulation and run -a runs the simulation.

Installing modelsim in Ubuntu 13.04 (Raring Ringtail)

Modelsim is an industrial standard HDL simulator.It can simulate VHDL, Verilog, SystemVerilog and SystemC.
Here I am descring the installation of modelsom altera starter edition in Ubuntu.
If is a free licence version of modelsim which would be a better starting point for a newbie.

1.You need to register on the site to download the package, so be patient and complete
   the registration process. Follow the link.

2.Now download the compressed installation package.  Follow the download link
   under ModelSim-Altera Starter Edition.



3.For windows installation .exe is provided and follow the steps as usual. For linux zip   file is provided.

  $ tar -xvf 12.1_modelsim_ase_linux.tar.gz

  It may not be set with the permission to execute, so make it executable and run.

  $ chmod +x script.sh ; ./script.sh

4.Enjoy coding !!